The present invention relates, in general, to semiconductor integrated circuits, and, more specifically, to a semiconductor integrated circuit and methods therefore capable of reducing leakage current and hence, power consumption by controlling the supply of power for an internal logic circuit in accordance with active state and sleep state of the internal circuit.
Increased power dissipation is becoming a major challenge in the design of integrated circuits. Increased power dissipation causes several problems including reducing battery life in mobile systems, expensive packaging and cooling solutions and can also result in chip failures. Of the various components contributing to power dissipation, leakage or static power dissipation is growing very fast and is predicted to exceed dynamic power dissipation in the near future.
Much effort has gone into investigating methods for reducing and controlling leakage in circuits. The multi-Vth technique (see Kuroda et al., “A 0.9 V, 150 MHz, 10 mW, 4 mm2, 2-DCT Core Processor with Variable VT Scheme,” IEEE J. Solid-State Circuits, vol. 31, pp. 1770-1778, November 1996, the disclosure of which is hereby incorporated by reference) uses high threshold circuits in non-critical areas and nominal or low threshold circuits in critical areas of the design. The body biasing technique (see Keshavarzi et al., “Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt CMOS ICs,” ISLPED 2001, the disclosure of which is hereby incorporated by reference) controls the body voltage to effectively raise the threshold voltage, in turn, reducing leakage in circuits. Also, since leakage power is directly proportional to the logic area, any technique which reduces area also reduces leakage. There are various synthesis algorithms which target leakage. Power gating (see Mutoh et al., “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, August 1995, the disclosure of which is hereby incorporated by reference) is another highly effective technique which uses sleep transistors to cut off the power supply to the logic circuit in an idle state.
Power gating is implemented by introducing one or more sleep transistors (could be a header transistor 12 which is typically a PFET, or a footer transistor 14 which is typically an NFET, or both) as shown in FIG. 1. When the logic circuitry 16 in FIG. 1 is in an idle state, the header/footer transistor is turned off by setting a sleep signal to logic state “1” (sleep_n to logic state “0”). This has the effect of reducing standby or leakage current by an order of magnitude.
Even though power gating is very effective in reducing leakage (reduces leakage by 90% or more) and seems like a simple idea, there are many difficulties in implementing power gating. Some of the more important problems in implementing power gating are listed below. Note that many of the problems arise because in the power gated state, latches lose their data and the outputs of the logic circuit being power gated assume an unknown state.    1. The state of the latches in the power gated logic circuit may need to be stored before turning off the power gating transistors and restored during power-up.    2. Since a power gated logic circuit loses its state, fence circuitry is required to interface the power gated logic with neighboring logic which is not power gated.    3. Power gating can affect the response time of the circuit negatively. The penalty may arise since one or more cycles may be required during power gating and power-up to store and restore the state. Additional cycles may also be required to power-up the logic over several cycles to minimize voltage swings on the power rails.    4. A power management unit to control the various power gating steps has to be designed. This can require significant effort. One of the issues to be considered is when to turn a unit on or off. Another complication arises if multiple units are power gated. In this case, the power management unit has to coordinate the change of state of the multiple units since turning multiple units on or off simultaneously could cause unacceptable noise on the power rails.    5. It can be seen from the previous items that power gating adds significant burden on verification—both functional as well at the circuit levels.
The problems enumerated above are overcome by use of a modification of the power gating technique, where the modification is named power gating with data retention using virtual rail voltage clamp (VRC) (see Kumagai, et al., “A Novel Powering-down Scheme for Low Vt CMOS Circuits,” IEEE Symposium on VLSI Circuits, 1998, and Kumagai et al., “Semiconductor Integrated Circuit Device with Low Power Consumption and Simple Manufacturing Steps”, U.S. Pat. No. 6,208,171, B1, Mar. 27, 2001, the disclosures of which are hereby incorporated by reference). However, the modification means that leakage reduction is sacrificed.
Some other related patents are M. Paris, “Technique for Efficient Logic Power Gating with Data Retention in Integrated Circuit Devices,” U.S. Pat. No. 6,512,394, issued on Jan. 28, 2003, and Notani et al., “Semiconductor Integrated Circuit,” U.S. Pat. No. 6,556,071, issued on Apr. 29, 2003, the disclosures of which are hereby incorporated by reference.
Power gating with a virtual rail voltage clamp can be seen in FIG. 2, where a generic voltage clamp 22 is shown in parallel to a power gating switch or footer 14. In FIG. 2, “Virtual ground” refers to a node or rail where the ground terminal of the logic circuit connects to the power gating device which in FIG. 2 is the drain of the NFET/footer. During power gating, since the footer switch 14 is off, the voltage at the drain of the footer rises and approaches Vdd/2, which causes the output signal “out” to assume an undetermined state if the output signal was initially at logic state “0”. The addition of a voltage clamp circuit 22 prevents the voltage at the virtual ground from rising above a certain value determined by the characteristic of the voltage clamp circuit and the leakage current from the logic circuit being gated. The maximum steady state voltage at the virtual ground rail in the presence of a virtual rail clamp device is referred to as Vclamp. If Vclamp is small enough, then the output state loss can be prevented. Some of the voltage clamp circuits found in the prior art literature are diodes or PFETs (see Kumagai et al., “Semiconductor Integrated Circuit Device with Low Power Consumption and Simple Manufacturing Steps,” U.S. Pat. No. 6,208,171, B1, Mar. 27, 2001, the disclosure of which is hereby incorporated by reference). Since powergating with VRC prevents state loss, many of the problems associated with powergating without VRC are overcome partially or fully but at the cost of increased leakage.